The present invention relates generally to static random access memory (SRAM) devices, and more particularly to an SRAM cell with a power saving module activated by word line signals for reducing leakage current.
SRAM is a type of memory device consisted of a latch storing a value, and pass-gate transistors controlling read/write operation of the latch. In order to ensure that an SRAM device functions properly, the minimum voltage (Vccmin) of a power supply needs to be higher than a predetermined level, which in turns demands a large layout area for an SRAM cell. However, the larger the SRAM cell, the more susceptible it is to leakage current. These conflicting constraints have posed challenges for SRAM designs.
One conventional approach to meeting the challenge is to provide a power saving controller for a bank of SRAM cells. The power saving controller is coupled to all of the source nodes of the SRAM cells in the bank. When the bank is selected for read/write operation, the power saving controller is inactivated and the source nodes of the SRAM cells are coupled to ground. When the bank is not selected, the power saving controller is activated to raise the voltage at the source nodes for all the SRAM cells in the unselected bank. As the voltage at the source nodes are raised, the voltage difference between the drains and sources of the SRAM cells are reduced, thereby reducing the leakage current there between.
The conventional scheme of leakage current reduction still has much room for improvement. The conventional power saving controller controls an entire bank, and does not discriminate among the SRAM cells therein. When a bank is selected, some of the cells may be subject to read/write operation, while others may not. The conventional power saving controller does not provide those unselected cells with an optimal design for reducing leakage current. Moreover, the conventional power saving controller is implemented as a circuit module external to the memory banks of an SRAM device. As the conventional power saving controller is designed to reduce leakage current for all the cells in the bank, it is usually turn out to be large in size and occupy excessive silicon real estate. This causes a design challenge, as the SRAM continues to scale down to 45 nm process and beyond.
As such, what is needed is a SRAM device with an optimal design for reducing leakage current under limited requirement for silicon real estate.